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Ethernet and MII management
The following figure shows the MII receive AC timing diagram.
RX_CLK
RXD[3:0]
RX_DV
t MRXH
t MRX
t MRXF
Valid Data
t MRXR
RX_ER
t MRDVKH
t MRDXKH
Figure 13. MII receive AC timing diagram
8.2.2
RMII AC timing specifications
This section describes the RMII transmit and receive AC timing specifications.
8.2.2.1
RMII transmit AC timing specifications
The following table provides the RMII transmit AC timing specifications.
Table 22. RMII transmit AC timing specifications
At recommended operating conditions with OV DD of 3.3 V ± 300mV.
Parameter/Condition
REF_CLK clock
REF_CLK duty cycle
REF_CLK to RMII data TXD[1:0], TX_EN delay
REF_CLK data clock rise V IL (min) to V IH (max)
REF_CLK data clock fall V IH (max) to V IL (min)
Symbol 1
t RMX
t RMXH /t RMX
t RMTKHDX
t RMXR
t RMXF
Min
—
35
2
1.0
1.0
Typical
20
—
—
—
—
Max
—
65
13
4.0
4.0
Unit
ns
%
ns
ns
ns
Note:
1. The symbols used for timing specifications follow the pattern of t (first three letters of functional block)(signal)(state)(reference)(state) for
inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, t RMTKHDX symbolizes RMII
transmit timing (RMT) for the time t RMX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in
general, the clock reference symbol representation is based on two to three letters representing the clock of a particular
functional. For example, the subscript of t RMX represents the RMII(RM) reference (X) clock. For rise and fall times, the latter
convention is used with the appropriate letter: R (rise) or F (fall).
The following figure provides the AC test load.
Output
Z 0 = 50 Ω
R L = 50 Ω
OV DD /2
Figure 14. AC test load
MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3
Freescale Semiconductor
25
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